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?2003 silicon storage technology, inc. s71151-04-000 11/03 397 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. mtp is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit (x8) many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 features: ? organized as 64k x8 / 128k x8 / 256k x8 / 512k x8 2.7-3.6v read operation superior reliability ? endurance: at least 1000 cycles ? greater than 100 years data retention low power consumption: ? active current: 10 ma (typical) ? standby current: 2 a (typical) fast read access time: ? 70 ns ? 90 ns latched address and data fast byte-program operation: ? byte-program time: 10 s (typical) ? chip program time: 0.6 seconds (typical) for sst37vf512 1.2 seconds (typical) for sst37vf010 2.4 seconds (typical) for sst37vf020 4.8 seconds (typical) for sst37vf040 electrical erase using programmer ? does not require uv source ? chip-erase time: 100 ms (typical) cmos i/o compatibility jedec standard byte-wide flash eeprom pinouts packages available ? 32-lead plcc ? 32-lead tsop (8mm x 14mm) ? 32-pin pdip product description the sst37vf512/010/020/040 devices are 64k x8 / 128k x8 / 256k x8 / 512k x8 cmos, many-time programmable (mtp), low cost flash, manufactured with sst?s proprietary, high performance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst37vf512/010/020/040 can be electrically erased and programmed at least 1000 times using an external programmer, e.g., to change the contents of devices in inventory. the sst37vf512/010/020/040 have to be erased prior to programming. these devices conform to jedec standard pinouts for byte-wide flash memories. featuring high performance byte-program, the sst37vf512/010/020/040 provide a typical byte-pro- gram time of 10 s. designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. data retention is rated at greater than 100 years. the sst37vf512/010/020/040 are suited for applications that require infrequent writes and low power nonvolatile storage. these devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use uv-eproms, otps, and mask roms. to meet surface mount and conventional through hole requirements, the sst37vf512/010/020/040 are offered in 32-lead plcc, 32-lead tsop, and 32-pin pdip packages. see figures 1, 2, and 3 for pin assignments. device operation the sst37vf512/010/020/040 devices are nonvolatile memory solutions that can be used instead of standard flash devices if in-system programmability is not required. it is functionally (read) and pin compatible with industry standard flash products.the device supports electrical erase operation via an external programmer. read the read operation of the sst37vf512/010/020/040 is controlled by ce# and oe#. both ce# and oe# have to be low for the system to obtain data from the outputs. once the address is stable, the address access time is equal to the delay from ce# to output (t ce ). data is available at the output after a delay of toe from the falling edge of oe#, assuming the ce# pin has been low and the addresses have been stable for at least t ce -t oe. when the ce# pin is high, the chip is deselected and a standby current of only 10 a (typical) is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is v ih. refer to figure 4 for the timing diagram. sst37vf512 / 010 / 020 / 0402.7v-read 512kb / 1mb / 2mb / 4mb (x8) mtp flash memories
2 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 byte-program operation the sst37vf512/010/020/040 are programmed by using an external programmer. the programming mode is acti- vated by asserting 11.4-12.6v on oe# pin and v il on ce# pin. the device is programmed using a single pulse (we# pin low) of 10 s per byte. using the mtp programming algorithm, the byte-program process continues byte-by- byte until the entire chip has been programmed. refer to figure 10 for the flowchart and figure 6 for the timing dia- gram. chip-erase operation the only way to change a data from a ?0? to ?1? is by electrical erase that changes every bit in the device to ?1?. the sst37vf512/010/020/040 use an electrical chip-erase operation. the entire chip can be erased in 100 ms (we# pin low). in order to activate erase mode, the 11.4-12.6v is applied to oe# and a 9 pins while ce# is low. all other address and data pins are ?don?t care?. the falling edge of we# will start the chip-erase operation. once the chip has been erased, all bytes must be verified for ffh. refer to figure 9 for the flowchart and figure 5 for the timing diagram. product identification mode the product identification mode identifies the devices as sst37vf512, sst37vf010, sst37vf020, and sst37vf040 and manufacturer as sst. this mode may be accessed by the hardware method. to activate this mode, the programming equipment must force v h (11.4- 12.6v) on address a 9 . two identifier bytes may then be sequenced from the device outputs by toggling address line a 0 . for details, see table 3 for hardware operation. design considerations the sst37vf512/010/020/040 should have a 0.1 f ceramic high frequency, low inductance capacitor con- nected between v dd and gnd. this capacitor should be placed as close to the package terminals as possible. oe# and a 9 must remain stable at v h for the entire dura- tion of an erase operation. oe# must remain stable at v h for the entire duration of the program operation. table 1: p roduct i dentification address data manufacturer?s id 0000h bfh device id sst37vf512 0001h c4h sst37vf010 0001h c5h sst37vf020 0001h c6h sst37vf040 0001h c2h t1.2 397 y-decoder i/o buffers 397 ill b1.1 address buffer x-decoder dq 7 - dq 0 memory address a 9 oe# ce# we# superflash memory control logic f unctional b lock d iagram
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 3 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 figure 1: p in a ssignments for 32- lead plcc figure 2: p in a ssignments for 32- lead tsop (8 mm x 14 mm ) 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a14 a13 a8 a9 a11 oe# a10 ce# dq7 4 3 2 1 32 31 30 a12 a15 nc nc v dd we# nc a12 a15 a16 nc v dd we# nc a12 a15 a16 nc v dd we# a17 a12 a15 a16 a18 v dd we# a17 32-lead plcc top view 397 ill f02a.3 14 15 16 17 18 19 20 dq1 dq2 v ss dq3 dq4 dq5 dq6 dq1 dq2 v ss dq3 dq4 dq5 dq6 dq1 dq2 v ss dq3 dq4 dq5 dq6 dq1 dq2 v ss dq3 dq4 dq5 dq6 sst37vf512 sst37vf010 sst37vf020 sst37vf040 sst37vf040 sst37vf020 sst37vf010 sst37vf512 sst37vf512 sst37vf010 sst37vf020 sst37vf040 sst37vf040 sst37vf020 sst37vf010 sst37vf512 a11 a9 a8 a13 a14 nc we# v dd nc nc a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 397 ill f01.0 standard pinout top view a11 a9 a8 a13 a14 nc we# v dd nc a16 a15 a12 a7 a6 a5 a4 a11 a9 a8 a13 a14 a17 we# v dd nc a16 a15 a12 a7 a6 a5 a4 a11 a9 a8 a13 a14 a17 we# v dd a18 a16 a15 a12 a7 a6 a5 a4 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 sst37vf040 sst37vf020 sst37vf010 sst37vf512 sst37vf512 sst37vf010 sst37vf020 sst37vf040
4 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 figure 3: p in a ssignments for 32- pin pdip table 2: p in d escription symbol pin name functions a ms 1 -a 0 1. a ms = most significant address a ms = a 15 for sst37vf512, a 16 for sst37vf010, a 17 for sst37vf020, and a 18 for sst37vf040 address inputs to provide memory addresses. dq 7 -dq 0 data input/output to output data during read cycles and receive input data during program cycles. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. we# write enable to program or erase (we# = v il pulse during program or erase) oe# output enable to gate the data output buffers during read operation when low v dd power supply to provide 3.0v supply (2.7-3.6v) v ss ground nc no connection unconnected pins. t2.1 397 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin pdip top view nc nc a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v dd we# nc a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v dd we# nc a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v dd we# a17 a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v dd we# a17 a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 sst37vf512 sst37vf010 sst37vf020 sst37vf040 sst37vf040 sst37vf020 sst37vf010 sst37vf512 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss 397 ill f02b.1
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 5 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 note: x = v il or v ih (or v h in case of oe# and a 9 ) v h = 11.4-12.6v table 3: o peration m odes s election mode ce# we# a 9 oe# dq address read v il v ih a in v il d out a in output disable v il xx v ih high z a in standby v ih xx x high z x chip-erase v il v il v h v h high z x byte-program v il v il a in v h d in a in program/erase inhibit x v ih xxhigh z x xxxv il or v ih high z/ d out x product identification v il v ih v h v il manufacturer?s id (bfh) device id 1 a ms 2 - a 1 =v il , a 0 =v il a ms 2 - a 1 =v il , a 0 =v ih t3.2 397 1. device id = c4h for sst37vf512, c5h for sst37vf020, c6h for sst37vf020, and c2h for sst37vf040 2. a ms = most significant address a ms = a 15 for sst37vf512, a 16 for sst37vf010, a 17 for sst37vf020, and a 18 for sst37vf040 absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 13.2v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w through hold lead soldering temperature (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300c surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange range ambient temp v dd commercial 0c to +70c 2.7-3.6v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 100 pf see figures 7 and 8
6 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 table 4: r ead m ode dc o perating c haracteristics v dd =2.7-3.6v (ta = 0c to +70c (commercial)) symbol parameter limits test conditions min max units i dd v dd read current address input=v ilt /v iht , at f=1/t rc min v dd =v dd max 12 ma ce#=v il, oe#=v iht , all i/os open i sb standby v dd current 15 a ce#=v ihc , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 0.7 v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.3 v i oh =-100 a, v dd =v dd min i h supervoltage current for a 9 200 a ce#=oe#=v il , a 9 =v h max t4.6 397 table 5: p rogram /e rase dc o perating c haracteristics v dd =2.7-3.6v (ta = 25c5c) symbol parameter limits test conditions min max units i dd v dd erase or program current 20 ma ce#=v il, oe#=v h , v dd =v dd max, we#=v il i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v h supervoltage for a 9 and oe# 11.4 12.6 v i h supervoltage current for a 9 and oe# 200 a oe#=v h max, a 9 =v h max, v dd =v dd max, ce# = v il t5.1 397 table 6: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t6.1 397 table 7: c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t7.0 397 table 8: r eliability c haracteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t8.3 397
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 7 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 ac characteristics table 9: r ead c ycle t iming p arameters v dd = 2.7-3.6v (ta = 0c to +70c (commercial)) symbol parameter sst37vf512-70 sst37vf010-70 sst37vf020-70 sst37vf040-70 sst37vf512-90 sst37vf010-90 sst37vf020-90 sst37vf040-90 units min max min max t rc read cycle time 70 90 ns t ce chip enable access time 70 90 ns t aa address access time 70 90 ns t oe output enable access time 35 45 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. ce# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t chz 1 ce# high to high-z output 30 30 ns t ohz 1 oe# high to high-z output 30 30 ns t oh 1 output hold from address change 0 0 ns t9.2 397 table 10: p rogram /e rase c ycle t iming p arameters v dd = 2.7-3.6v (ta = 25c5c) symbol parameter min max units t bp byte-program time 12 20 s t ces ce# setup time 1 ns t ceh ce# hold time 1 ns t as address setup time 1 ns t ah address hold time 1 ns t ds data setup time 1 ns t dh data hold time 1 ns t prt oe# rise time for program and erase 1 ns t vps oe# setup time for program and erase 1 ns t vph oe# hold time for program and erase 1 ns t pw we# program pulse width 10 15 ns t ew we# erase pulse width 100 500 ns t vr oe#/a 9 recovery time for erase 1 ns t art a 9 rise time to 12v during erase 1 ns t a9s a 9 setup time during erase 1 ms t a9h a 9 hold time during erase 1 ms t10.0 397
8 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 figure 4: r ead c ycle t iming d iagram figure 5: c hip -e rase t iming d iagram 397 ill f03.0 address dq 7-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 397 ill f04.0 t a9h t vr t vph t vps t ceh t prt v dd v ss oe# a 9 we# v h v h v ih v il dq 7-0 ce# address (except a 9 ) t a9s t art t ces t ew
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 9 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 figure 6: b yte -p rogram t iming d iagram 397 ill f05.0 data valid address valid t ah t ceh t as t ds t dh v dd v h high-z v ss t ces t pw t vph t prt t vps oe# we# dq 7-0 ce# address t pc
10 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 figure 7: ac i nput /o utput r eference w aveforms figure 8: a t est l oad e xample 397 ill f06.1 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 397 ill f07.1 to tester to dut c l
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 11 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 figure 9: c hip -e rase a lgorithm start a 9 = v h , oe# = v h oe#/a 9 = v il or v ih ce# = v il wait t vr recovery time erase 100ms pulse (we# = v il ) read device device passed compare all bytes to ff device failed 397 ill f08.0 we# = v ih no ye s
12 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 figure 10: b yte -p rogram a lgorithm *see figure 9 start erase* oe# = v h address = first location; load data ce# = v il oe# = v il program 10s pulse (we# = v il ) read device device passed compare all bytes to original data increment address device failed 397 ill f09.1 last address? wait t vr no no ye s ye s
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 13 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 product ordering information environmental attribute e = non-pb package modifier h = 32 pins or leads package type n = plcc p = pdip w = tsop (type 1, die up, 8mm x 14mm) operating temperature c = commercial = 0 to +70c minimum endurance 3 = 1,000 cycles read access speed 70 = 70 ns 90 = 90 ns device density 040 = 4 mbit 020 = 2 mbit 010 = 1 mbit 512 = 512 kbit voltage v = 2.7-3.6v product series 37 = many-time programmable flash flash memories with flash pinout sst 37 vf 040 - 70 - 3c - nh e xx x x xxxx -xxx -x x -xx x x
14 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 valid combinations for sst37vf512 sst37vf512-70-3c-nh* sst37vf512-70-3c-wh* sst37vf512-70-3c-nhe* sst37vf512-70-3c-whe* sst37vf512-90-3c-nh* sst37vf512-90-3c-wh* sst37vf512-90-3c-ph* sst37vf512-90-3c-nhe* sst37vf512-90-3c-whe* valid combinations for sst37vf010 sst37vf010-70-3c-nh sst37vf010-70-3c-wh sst37vf010-70-3c-nhe sst37vf010-70-3c-whe sst37vf010-90-3c-nh ? sst37vf010-90-3c-wh ? sst37vf010-90-3c-ph sst37vf010-90-3c-nhe ? SST37VF010-90-3C-WHE ? valid combinations for sst37vf020 sst37vf020-70-3c-nh sst37vf020-70-3c-wh sst37vf020-70-3c-nhe sst37vf020-70-3c-whe sst37vf020-90-3c-nh ? sst37vf020-90-3c-wh ? sst37vf020-90-3c-ph sst37vf020-90-3c-nhe ? sst37vf020-90-3c-whe ? valid combinations for sst37vf040 sst37vf040-70-3c-nh sst37vf040-70-3c-wh sst37vf040-70-3c-nhe sst37vf040-70-3c-whe sst37vf040-90-3c-nh ? sst37vf040-90-3c-wh ? sst37vf040-90-3c-ph sst37vf040-90-3c-nhe ? sst37vf040-90-3c-whe ? note: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations. * not recommended for new designs. ? these 90 ns parts will be phased out and replaced by 70 ns parts in 2004. customers should use 70 ns parts for new designs and qualifications.
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 15 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 packaging diagrams 32- lead p lastic l ead c hip c arrier (plcc) sst p ackage c ode : nh .040 .030 .021 .013 .530 .490 .095 .075 .140 .125 .032 .026 .032 .026 .029 .023 .453 .447 .553 .547 .595 .585 .495 .485 .112 .106 .042 .048 .048 .042 .015 min. top view side view bottom view 1 232 .400 bsc 32-plcc-nh-3 note: 1. complies with jedec publication 95 ms-016 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc .050 bsc optional pin #1 identifier .020 r. max. r. x 30?
16 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 32- lead t hin s mall o utline p ackage (tsop) 8 mm x 14 mm sst p ackage c ode : wh 32-tsop-wh-7 note: 1. complies with jedec publication 95 mo-142 ba dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm pin # 1 identifier 12.50 12.30 14.20 13.80 0.70 0.50 8.10 7.90 0.27 0.17 0. 50 bsc 1.05 0.95 0.15 0.05 0.70 0.50 0?- 5? detail
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit many-time programmable flash sst37vf512 / sst37vf010 / sst37vf020 / sst37vf040 17 ?2003 silicon storage technology, inc. s71151-04-000 11/03 397 32- pin p lastic d ual i n - line p ins (pdip) sst p ackage c ode : ph table 11: r evision h istory number description date 02 2002 data book feb 2002 03 part number changes - see page 14 for additional information clarified the test conditions for v dd read current parameter in table 4 on page 6 ? address input = v ilt /v iht ?ce#=oe#=v ilt mar 2003 04 2004 data book added non-pb mpns and removed footnote (see page 14) nov 2003 32-pdip-ph-3 pin #1 identifier c l 32 1 base plane seating plane note: 1. complies with jedec publication 95 mo-015 ap dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .010 inches. .200 .170 7? 4 plcs. .600 bsc .100 bsc .150 .120 .022 .016 .065 .045 .080 .070 .050 .015 .075 .065 1.655 1.645 .012 .008 0? 15? .625 .600 .550 .530 silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com

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